Ohayashi, M.: search on Z-Library

The world's largest scientific articles store. 70,000,000+ articles for free.

Don't use scam websites

1

A new MOS-gate bipolar transistor for power switches

Tanaka, T., Yasuda, Y., Ohayashi, M.

Journal:

IEEE Transactions on Electron Devices

Year:

1986

Language:

english

File:

PDF, 771 KB

english, 1986

2

A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates

Tamba, N., Anzai, A., Akimoto, K., Ohayashi, M., Hiramoto, T., Kokubu, T., Ohmori, S., Muraya, T., Kishimoto, A., Tsuji, S., Hayashi, H., Handa, N., Igarashi, T., Nambu, H., Yoshida, M., Fujiwara, T.,

Journal:

IEEE Journal of Solid-State Circuits

Year:

1994

Language:

english

File:

PDF, 860 KB

english, 1994

3

A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM

Nambu, H., Kanetani, K., Idei, Y., Masuda, T., Higeta, K., Ohayashi, M., Usami, M., Yamaguchi, K., Kikuchi, T., Ikeda, T., Ohhata, K., Kusunoki, T., Homma, N.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1995

Language:

english

File:

PDF, 861 KB

english, 1995

4

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry

Higeta, K., Usami, M., Ohayashi, M., Fujimura, Y., Nishiyama, M., Isomura, S., Yamaguchi, K., Idei, Y., Nambu, H., Ohhata, K., Hanta, N.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1996

Language:

english

File:

PDF, 930 KB

english, 1996

5

[IEEE 1994 IEEE Symposium on VLSI Circuits - Honolulu, HI (JUNE 9-11, 1994)] Proceedings of 1994 IEEE Symposium on VLSI Circuits - A 0.65ns, 72kb Ecl-cmos Ram Macro For A 1mb Sram

Nambu, H., Kanetani, K., Idei, Y., Masuda, T., Higeta, K., Ohayashi, M., Usami, M., Yamaguchi, K., Kikuchi, T., Ikeda, T., Ohhata, K., Kusunoki, T., Homma, N.

Year:

1994

Language:

english

File:

PDF, 251 KB

english, 1994

6

[IEEE Bipolar/Bicmos Circuits and Technology Meeting - Minneapolis, MN, USA (2-3 Oct. 1995)] Proceedings of Bipolar/Bicmos Circuits and Technology Meeting - A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry

Higeta, K., Usami, M., Ohayashi, M., Fujimura, Y., Nishiyama, M., Isomura, S., Yamaguchi, K., Idei, Y., Nambu, H., Ohhata, K., Hanta, N.

Year:

1995

Language:

english

File:

PDF, 358 KB

english, 1995